The following table describes the functions of the signals on the QUUB stackplane.
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Pin
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Name
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Description
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1
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#DBG
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Asserted by the MCU when the debugger is selected, to be used to hi-Z signals on a stackable that share signals with the debugger, most notably RX0 and D0-3.
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2
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GND
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System GND or 0V.
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3-10
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D0-7
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Data signals, can be set to input or output in any combination under program control. D0-3 are also connected to the debugging header and can be used to 'talk' to hardware and/or test instruments on the debugger.
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11
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SENSE
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This signal is used to detect a bus clash if two or more stackables have the same address set. It is pulled up to VCC by a 100k 1% resistor on the main board and should be pulled down to GND by the same value resistor in any stackable that is selected. The result is a voltage divider that will pull the signal to VCC if no stackable is being addressed, 1/2 VCC if a single stackable is being addressed, and a value less than 1/2 VCC if two or more stackables are being addressed. Thus the MCU can detect bus clashes caused by multiple stackables being set to the same address.
Connected indirectly via an analogue MUX to the MCU's ADC0 input (pin 31). This MUX also connects all the seven dockable ADC signals.
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12
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ADC0
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A direct input to the MCU's ADC0 input (pin 31). Not to be used for accurate analogue readings due to the noisy environment, but useful for simple things like light level detection.
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13
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#RST
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The system reset signal. This is not connected to the reset pushbutton, it is a signal under control of the MCU and as such can be asserted by any running program without affecting the hardware MCU on the main PCB. This signal is pulled DOWN by a resistor on the QUUB board, so all stackplane hardware will be held in a reset condition until the main program is up and running and it releases the signal.
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14
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#FLT-SP
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This is a fault signal that can be asserted by any stackable. Like all the fault signals it can be masked under program control.
This signal must be actively driven low and released to a hi-Z state when not asserted. As such any module that uses this signal must implement the connection with an open-collector/drain interface or equivelant.
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15
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#FAULT
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Any non-masked fault signals that get asserted will assert this signal. It can also be asserted by hardware on a debugging attachment. If this signal is asserted by any source it will shut down the 3V3 power to the stackplane and most of the hardware on the QUUB board. Some critical hardware will remain powered in this situation.
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16
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#SPE
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Stackplane enable. The address and data signals are only valid when this signal is asserted.
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17
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#ACK
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Interrupt ackowledge. When asserted the address signals are set to inputs and an interrupting module can place an interrupt vector onto them. Note that with the vector signals any low bit must be driven low and high bits must float. IE use open-collector drivers or a similar arrangment.
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18
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#INT
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System interrupt signal. This is a direct input to the MCU pin 19) and is used to interrupt the program flow and invoke the interrupt handler. The handler can then (optionally) read the vector from A0-3 and SA0-3 and act accordingly.
This signal must be actively driven low and released to a hi-Z state when not asserted. As such any module that uses this signal must implement the connection with an open-collector/drain interface or equivelant.
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19
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#EEP
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When asserted the MCU is attempting to read the EEPROM on a stackable. Each stackable should OR this with their internal #SEL signal to enable their onboard configuration EEPROM in favour of any other devices on the board.
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20-23
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A0-3
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Address signals. These are to be compared with a local address switch by each stackable and the result used as a select signal to enable the stackable. Address #0 is reserved for a virtual stackable on the MCU board, so only 15 stackables can be addressed.
Only valid when in address mode #SPE is asserted.
These signals can also be used by stackables to provide the high nibble of an 8-bit interrupt vector, in which case they will be sampled when #ACK is asserted by the MCU.
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24-27
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SA0-3
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Sub address signals. These are to be used by stackables to select any onboard devices. Up to 16 such devices can be addressed on each stackable. Only valid when #SPE is asserted.
These signals can also be used by stackables to provide the low nibble of an 8-bit interrupt vector, in which case they will be sampled when #ACK is asserted by the MCU.
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28
|
MISO
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The system SPI input signal. All modules on the system that use this signal MUST hi-Z their output if not selected. SPI is also connected to the debugging header.
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29
|
MOSI
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The system SPI output signal.
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30
|
CLK
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The system SPI clock signal.
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31
|
TX1
|
UART1 transmit output.
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32
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RX1
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UART1 receive input.
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33
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TX0
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UART0 transmit. Also connected to the debugging header.
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34
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RX0
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UART0 receive input. Also connected to the debugging header. If used by the debugger then it should not be used by anything else on the system unless this signal is tristated by any other RX0 source when the debugger is selected. Use the #DBG signal to do this disabling on a stackable.
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35
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SCL0
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The I2C0 channel's clock signal. Connected directly to the MCU (pin 7) but also has an active pullup device to increase the allowable bus capacitance, and therefore the usable lenght of the I2C bus. Also connected to the QUUBlink and PiicoDEV/STEMMA-QT/QWIIC busses.
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36
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SDA0
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The I2C0 channel's data signal. As SCL0 but connected to pin 6.
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37
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VBAT
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A power signal sourced by a backup battery if one is installed on the system.
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38
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3V3
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A regulated 3V3 power signal. If no other PSU modules are installed and the system is running from the USB cable plugged into the Pico then this connects indirectly to pin 36 on the Pico through a perfect diode and an analogue switch. This switch is under program control plus it will automatically shut the power down if the current draw exceeds 500mA. This scenariio will also cause a #FAULT assertion.
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39
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5V0
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A regulated 5V0 power signal. Only available at a full 5V if a PSU module provides it as such, if the system is running from the USB cable conected to the Pico this will be 5V minus one diode drop.
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40
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12V
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This is an unregulated 12V power signal to be used for devices that need more power and/or a higher voltage, say an alram horn. The 12V value is nominal as typically it would be connected to a battery that is undergoing charge/discharge cycles so the voltage may vary considerably, from about 11V to over 14V.
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